IC42S16102
60-BALL VF-BGA ( 16M SDRAM )
7
6
5
4
3
2
1
VDD
A1
A2
A10
NC
CS
CAS
WE
NC
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
VDD
A3
A0
NC
NC
RAS
LDQM
NC
NC
VSSQ
VDDQ
DQ4
VSSQ
V
DDQ
DQ0
A4
A5
A7
A9
NC
CLK
UDQM
NC
NC
VDDQ
VSSQ
DQ
11
VDDQ
VSSQ
DQ
15
VSS
A6
A8
A11
CKE
NC
NC
NC
DQ8
DQ9
DQ
10
DQ
12
DQ
13
DQ
14
VSS
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
PIN DESCRIPTIONS
A0 - A10
A11
DQ0 - DQ15
CLK
CKE
CS
RAS
CAS
WE
LDQM,UDQM
V
DD
/V
SS
V
DD
Q/V
SS
Q
NC
Address
Bank Address
Data Input/Output
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
Row Address : RA0 - RA11, Column Address : CA0 - CA7
Auto-precharge flag : A10
Selects bank to be activated during
RAS
activity
Selects bank to be read/written during
CAS
activity
Multiplexed data input / output pin
The system clock input.All other inputs are registered to the SDRAM
on the rising edge of CLK
Controls internal clock signal and when deactivated,the SDRAM will
be one of the states among power down,suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
RAS,CAS
and
WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Power supply for internal circuits and input buffers
Power supply for output buffers
No Connection
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005
3
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
