IC42S16102
AC CHARACTERISTICS
(1,2,3)
-5
Symbol
t
CK
3
t
CK
2
t
AC
3
t
AC
2
t
CHI
t
CL
t
OH
t
LZ
t
HZ
3
t
HZ
2
t
DS
t
DH
t
AS
t
AH
t
CKS
t
CKH
t
CKA
t
CS
t
CH
t
RC
t
RAS
t
RP
t
RCD
t
RRD
t
DPL
Parameter
Clock Cycle Time
Access Time From CLK
(4)
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
Output LOW Impedance Time
Output HIGH Impedance Time
(5)
CAS
Latency = 3
CAS
Latency = 2
CAS
Latency = 3
CAS
Latency = 2
Min.
Max.
Min.
5
—
7
—
—
4.5
—
5
2
—
2
—
2
—
0
—
—
4.5
—
5
2
—
1
—
2
—
1
—
2
—
1
—
1CLK+3 —
2
—
1
—
50
—
30 100,000
15
—
15
—
10
—
2CLK —
2CLK+t
RP
—
1
—
10
64
-6
Max.
Min.
6
—
8
—
—
5.5
—
6
2
—
2
—
2
—
0
—
—
5.5
—
6
2
—
1
—
2
—
1
—
2
—
1
—
1CLK+3 —
2
—
1
—
60
—
36 100,000
18
—
18
—
12
—
2CLK —
2CLK+t
RP
—
1
—
10
64
-7
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
7
—
8.6
—
—
6
—
6
2.5
—
2.5
—
2
—
0
—
—
6
—
6
2
—
1
—
2
—
1
—
2
—
1
—
1CLK+3 —
2
—
1
—
70
—
42 100,000
21
—
21
—
14
—
2CLK —
2CLK+t
RP
—
1
—
10
64
CAS
Latency = 3
CAS
Latency = 2
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
CKE to CLK Recovery Delay Time
Command Setup Time (CS,
RAS, CAS, WE,
DQM)
Command Hold Time (CS,
RAS, CAS, WE,
DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
Input Data To Precharge
Command Delay time
t
DAL
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
t
T
Transition Time
t
REF
Refresh Cycle Time (4096)
Notes:
1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated
voltages. Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and
V
IL
(max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.) when the output is in the high impedance state.
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005
7
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
