IS61C512
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
Symbol
Parameter
Write Cycle Time
CE1
to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
-15 ns
Min. Max.
15
12
12
12
0
0
10
8
0
—
2
—
—
—
—
—
—
—
—
—
7
—
-20 ns
Min. Max.
20
15
15
15
0
0
12
10
0
—
2
—
—
—
—
—
—
—
—
—
10
—
-25 ns
Min. Max.
25
20
20
20
0
0
15
12
0
—
2
—
—
—
—
—
—
—
—
—
12
—
-35 ns
Min. Max.
35
30
30
30
0
0
20
15
0
—
2
—
—
—
—
—
—
—
—
—
8
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
t
SCE
1
t
SCE
2
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(2)
WE
LOW to High-Z Output
t
LZWE
(2)
WE
HIGH to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WE
WRITE CYCLE NO. 1 (WE Controlled)
(1,2)
t
WC
ADDRESS
t
SCE1
t
HA
CE1
t
SCE2
CE2
t
AW
t
PWE
t
SA
t
HZWE
HIGH-Z
WE
t
LZWE
D
OUT
DATA UNDEFINED
t
SD
t
HD
D
IN
DATA-IN VALID
6
Integrated Circuit Solution Inc.
SR011-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
