IS61C512
WRITE CYCLE NO. 2 (CE1 CE2 Controlled)
(1,2)
CE1,
CE1
t
WC
ADDRESS
t
SA
t
SCE1
t
HA
CE1
t
SCE2
CE2
t
AW
t
PWE
WE
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
t
HD
D
IN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if
OE
= HIGH.
Integrated Circuit Solution Inc.
SR011-0B
7