IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles
(5)
t
RC
ADDR
t
AA
(4)
t
ACE
t
AOE
OE
(4)
(4)
CE
R/W
t
LZ
DATA
OUT
(1)
t
OH
VALID DATA
(4)
t
HZ
(2)
BUSY
OUT
t
BDD
(3,4)
2940 drw 07
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE.
2. Timing depends on which signal is de-asserted first
CE
or
OE.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
Timing of Power-Up Power-Down
CE
I
CC
I
SB
2940 drw 08
t
PU
t
PD
,
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
