IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
CE
TIMING
(1)
ADDR
L and R
ADDRESSES MATCH
CE
R
t
APS
CE
L
t
BAC
t
BDC
BUSY
L
2654 drw 12
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only).
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS
(1)
t
RC
OR t
WC
ADDR
'A'
t
APS
ADDR
'B'
t
BAA
t
BDA
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
BUSY
'B'
2654 drw 13
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If
t
APS
is not satisified, the
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
BUSY
will be asserted (70121 only).
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
70121X25
70125X25
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Symbol
Parameter
Interrupt Timing
t
AS
Address Set-up Time
t
WR
Write Recovery Time
t
INS
Interrupt Set Time
t
INR
Interrupt Reset Time
NOTE:
1. "X" in part numbers indicates power rating (S or L).
Min. Max. Min. Max. Min. Max. Min. Max. Unit
0
0
—
—
—
—
25
25
0
0
—
—
—
—
25
35
0
0
—
—
—
—
40
40
0
0
—
—
—
—
45
45
ns
ns
ns
ns
2654 tbl 11
6.10
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
