IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(4)
70121X25
70125X25
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Symbol
Parameter
Write Cycle
Write Cycle Time
(3)
t
WC
t
EW
Chip Enable to End-of-Write
t
AW
Address Valid to End-of-Write
t
AS
Address Set-up Time
t
WP
Write Pulse Width
(6)
t
WR
Write Recovery Time
t
DW
Data Valid to End-of-Write
t
HZ
Output High-Z Time
(1,2)
t
DH
Data Hold Time
(5)
t
WZ
Write Enabled to Output in High-Z
(1,2)
t
OW
Output Active from End-of-Write
(1,2)
Min. Max. Min. Max. Min. Max. Min. Max. Unit
25
20
20
0
20
0
12
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
35
30
30
0
30
0
20
—
0
—
0
—
—
—
—
—
—
—
15
—
15
—
45
35
35
0
35
0
20
—
0
—
0
—
—
—
—
—
—
—
20
—
20
—
55
40
40
0
40
0
20
—
0
—
0
—
—
—
—
—
—
—
30
—
30
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
2654 tbl 09
1. Transition is measured
±500mV
from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, t
WC
= t
BAA
+ t
WP,
since R/
W
= V
IL
must occur after t
BAA
.
4. “X” in part numbers indicates power rating (S or L).
5. The specified t
DH
must be met by the device supplying write date to the RAM under all operating conditions.Although t
DH
and t
ow
values will vary over voltage
and temperature. The actual t
DH
will always be smaller than the actual t
OW.
6. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP.
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
CONTROLLED TIMING
(1,5,8)
t
WC
ADDRESS
t
HZ
(7)
OE
t
AW
(3)
t
WR
(2)
(7)
CE
R/
W
t
AS
(6)
t
WP
t
HZ
t
WZ
DATA
OUT
(4)
(7)
t
OW
(4)
t
DW
DATA
IN
t
DH
NOTES:
2654 drw 07
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
= V
IL
and a R/
W
= V
IL
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
6.10
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
