IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1,2,4)
t
RC
ADDRESS
t
AA
tOH
t
OH
PREVIOUS DATA VALID
DATA VALID
DATAOUT
BUSYOUT
2654 drw 05
(3,4)
t
BDD
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5,6)
tACE
CE
OE
(2)
HZ
(4)
t
tAOE
(2)
(1)
tHZ
tLZ
VALID DATA
DATAOUT
(1)
(4)
tLZ
tPD
tPU
ICC
CURRENT
50%
50%
ISS
2654 drw 06
NOTES:
1. Timing depends on which signal is aserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing
a write operation to the same address location. For simultanious read operations
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, and the address is valid prior to other coincidental with CE transition Low.
6. R/W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low.
6.10
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
