IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
CONTROLLED TIMING
(1,5,8)
t
WC
ADDRESS
t
HZ
(7)
OE
t
AW
CE
or
SEM
(9)
UB
or
LB
(9)
t
AS
(6)
R/
t
WP
(2)
t
WR
(3)
W
t
WZ
(7)
t
OW
(4)
(4)
DATA
OUT
t
DW
DATA
IN
t
DH
2683 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
,
UB
,
LB
CONTROLLED TIMING
(1,5)
t
WC
ADDRESS
t
AW
CE
or
SEM
(9)
t
AS
(6)
t
EW (2)
t
WR(3)
UB
or
LB
(9)
R/
W
t
DW
t
DH
DATA
IN
2683 drw 10
NOTES:
1. R/
W
or
CE
or
UB
&
LB
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a Low
UB
or
LB
and a Low
CE
and a Low R/
W
for memory array writing cycle.
3. t
WR
is measured from the earlier of
CE
or R/
W
(or
SEM
or R/
W
) going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE
, R/
W
, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with Output
Test Load (Figure 2).
8. If
OE
is Low during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is High during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
WP
.
9. To access RAM,
CE
= V
IL,
UB
or
LB
=
V
IL,
and
SEM
= V
IH.
To access Semaphore,
CE
= V
IH
or
UB
&
LB
=
V
IL,
and
SEM
= V
IL.
t
EW
must be met
for either condition.
6.16
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
