IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
t
RC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
t
AOE
(4)
tABE
UB, LB
R/W
t
OH
(1)
t
LZ
VALID DATA(4)
DATAOUT
BUSYOUT
NOTES:
(2)
tHZ
(3, 4)
2683 drw 07
t
BDD
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CE
tPU
tPD
ICC
50%
50%
ISB
2683 drw 08
6.16
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
