IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(5)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
t
OH
DATA VALID
BUSY
OUT
t
BDD
(3,4)
2746 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(5)
t
ACE
CE
t
AOE
OE
t
LZ
DATA
OUT
t
PU
CURRENT
I
CC
50%
I
SB
50%
2746 drw 08
(1)
(4)
(4)
t
HZ
(2)
t
HZ
(2)
VALID DATA
t
PD
t
LZ
(1)
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE.
2. Timing depends on which signal is deasserted first,
OE
or
CE.
3. t
BDD
delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations,
BUSY
has no
relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, t
AOE
, t
ACE
, t
AA,
or t
BDD
.
5. R/W = V
IH
, and the address is valid prior to or coincidental with
CE
transition LOW.
6.42
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
