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IDT7133SA35J 参数 Datasheet PDF下载

IDT7133SA35J图片预览
型号: IDT7133SA35J
PDF下载: 下载PDF文件 查看货源
内容描述: HIGH -SPEED 2K ×16的CMOS双口静态RAM [HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS]
分类和应用:
文件页数/大小: 16 页 / 141 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
7133X20
7143X20
Com'l Only
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
Write Cycle Time
(3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1,2)
Data Hold Time
(4)
Write Enable to Output in High-Z
(1,2)
Output Active from End-of-Write
(1,2,4)
20
15
15
0
15
0
15
____
____
7133X25
7143X25
Com'l, Ind
& Military
Min.
Max.
7133X35
7143X35
Com'l, Ind
& Military
Min.
Max.
Unit
Parameter
Min.
Max.
25
20
20
0
20
0
15
____
____
35
25
25
0
25
0
20
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2746 tbl 11a
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
12
____
15
____
20
____
0
____
0
____
0
____
12
____
15
____
20
____
0
0
0
7133X45
7143X45
Com'l &
Military
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
Write Cycle Time
(3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1,2)
Data Hold Time
(4)
Write Enable to Output in High-Z
(1,2)
Output Active from End-of-Write
(1,2,4)
45
30
30
0
30
0
20
____
____
7133X55
7143X55
Com'l, Ind
& Military
Min.
Max.
7133X70/90
7143X70/90
Com'l &
Military
Min.
Max.
Unit
Parameter
Min.
Max.
55
40
40
0
40
0
25
____
____
70/90
50/50
50/50
0/0
50/50
0/0
30/30
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2746 tbl 11b
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
20
____
20
____
25/25
____
5
____
5
____
5/5
____
20
____
20
____
25/25
____
5
5
5/5
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage from the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. For MASTER/SLAVE combination, t
WC
= t
BAA
+ t
WR
+ t
WP
, since R/W = V
IL
must occur after t
BAA.
4. The specification for t
DH
must be met by the device supplying write data to the RAM under all operation conditions. Although t
DH
and t
OW
values will very over voltage and
temperature, the actual t
DH
will always be smaller than the actual t
OW
.
5. 'X' in part number indicates power rating (SA or LA).
9
6.42