IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
t
OH
OE
t
OLZ
CS
2
t
ACS2
t
CLZ2
(5)
t
OE
(5)
t
CHZ2
(5)
CS
1
t
ACS1
t
CLZ1
DATA
OUT
(5)
t
OHZ (5)
t
CHZ1
DATA VALID
2967 drw 05
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
DATA VALID
2967 drw 06
t
OH
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
CS
1
CS
2
t
ACS2
t
CLZ2 (5)
t
ACS1
t
CLZ1 (5)
DATA
OUT
I
CC
POWER
SUPPLY
CURRENT I
SB
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
1
is LOW
,
CS
2
is HIGH.
3. Address valid prior to or coincident with
CS
1
transition LOW and CS
2
transition HIGH.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state.
t
CHZ2
t
CHZ1
DATA VALID
(5)
(5)
t
PU
t
PD
2967 drw 07
6.1
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
