IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 6)
t
WC
ADDRESS
CS
2
CS
1
t
AW
t
AS
t
WR1(3)
WE
(4)
t
WP
(6)
t
OW(7)
DATA
OUT
t
WHZ (7)
DATA
IN
t
DW
DATA VALID
2967 drw 08
t
DH1, 2
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1, 2)
t
WC
ADDRESS
t
AS
CS
2
t
CW
t
WR1
(3)
t
WR2
(3)
CS
1
(5)
t
AW
WE
t
DW
DATA
IN
t
DH1,2
DATA VALID
2967 drw 09
NOTES:
1.
WE
,
CS
1
or CS
2
must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW
WE
, a LOW
CS
1
and a HIGH CS
2
.
3. t
WR1, 2
is measured from the earlier of
CS
1
or
WE
going HIGH or CS
2
going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the
CS
1
LOW transition or CS
2
HIGH transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6.
OE
is continuously HIGH. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+t
DW
) to allow the
I/O drivers to turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not
apply and the minimum write pulse width is as short as the specified t
WP
.
7. Transition is measured
±200mV
from steady state.
6.1
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
