IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Data Retention Waveform
DATA RETENTION MODE
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
CC
V
DR ≥
V
2.0V
3.0V
3.0V
1.5V
CDR
R
t
t
Figures 1 and 2
DR
V
CE
3026 tbl 08
IH
V
IH
V
,
3026 drw 04
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
435
BUSY
435
Ω
Ω
INT
30pF
5pF
3026 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
AC Electrical Characteristics Over the
OperatingTemperatureSupplyVoltageRange(2)
71V321X25
71V421X25
Com'l
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
RC
t
Read Cycle Time
25
35
55
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
tAA
tACE
tAOE
tOH
tLZ
Address Access Time
25
25
35
35
55
55
____
____
____
____
____
____
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
12
20
25
____
____
____
3
3
3
____
____
____
0
0
0
Output High-Z Time(1,2)
12
15
30
____
____
____
tHZ
tPU
tPD
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
0
____
____
____
____
____
____
50
50
50
ns
3026 tbl 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
5
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
