IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
71V321X25
71V421X25
Com'l
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time(5 )
Chip Enable to End-of-Write
25
20
20
0
35
30
30
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
tWP
tWR
tDW
tHZ
20
0
30
0
40
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3 )
12
20
20
____
____
____
12
15
30
____
____
____
tDH
tWZ
tOW
0
0
0
(1,2)
____
____
____
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2)
15
15
30
____
____
____
0
0
0
ns
3026 tbl 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part numbers indicates power rating (S or L).
5. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
7
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
