IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with
BUSY
(4)
t
WP
R/W
"A"
t
WB
(3)
BUSY
"B"
t
WH
R/W
"B"
(2)
(1)
,
NOTES:
1. t
WH
must be met for both
BUSY
input (71V421, slave) or output (71V321, master).
2.
BUSY
is asserted on port 'B' blocking R/W
'B'
, until
BUSY
'B'
goes HIGH.
3. t
WB
is for the slave version (71V421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
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Timing Waveform of
BUSY
Arbitration Controlled by
CE
Timing
(1)
ADDR
"A" AND "B"
CE
"B"
t
APS
(2)
CE
"A"
t
BAC
BUSY
"A"
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ADDRESSES MATCH
t
BDC
Timing Waveform of
BUSY
Arbritration Controlled
by Address Match Timing
(1)
t
RC
ADDR
"A"
t
APS
(2)
ADDR
"B"
t
BAA
BUSY
"B"
3026 drw 13
OR
t
WC
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
t
BDA
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t
APS
is not satisified, the
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
BUSY
will be asserted (71V321 only).
10
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
