IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
beingexpandedindepth,thentheBUSYindicationfortheresultingarray
ꢀunctionalDescription
requires the use of an external AND gate.
TheIDT7V1321/IDT71V421providestwoportswithseparatecontrol,
addressandI/Opinsthatpermitindependentaccessforreadsorwrites
toanylocationinmemory.TheIDT71V321/IDT71V421hasanautomatic
power down feature controlled by CE. The CE controls on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
whennotselected(CE=VIH).Whenaportisenabled,accesstotheentire
memoryarrayispermitted.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganSRAMarrayinwidthwhileusingBUSYlogic,one
masterpartis usedtodecidewhichsideoftheSRAMarraywillreceive
a BUSY indication. Any number of slaves to be addressed in the same
addressrangeasthemaster,usetheBUSYsignalasawriteinhibitsignal.
ThusontheIDT71V321/IDT71V421SRAMstheBUSYpinisanoutput
ifthepartisMaster(IDT71V321),andtheBUSYpinisaninputifthepart
is a Slave (IDT71V421) as shown in Figure 3.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessage center)is assignedtoeachport. The leftportinterruptflag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), whereawriteisdefinedastheCER =R/WR=VILperTruthTable
II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag(INTR)isassertedwhentheleftportwritestomemorylocation7FF
(HEX)andtocleartheinterruptflag(INTR),therightportmustaccessthe
memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,
address locations 7FEand7FFare notusedas mailboxes, butas part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
SLAVE
Dual Port
RAM
MASTER
Dual Port
RAM
CE
CE
BUSYR
BUSYR
BUSYL
BUSYL
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSYL
BUSYL
BUSYR
BUSYR
BUSY
R
BUSY
L
3026 drw 16
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesabusyindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
TheuseofBUSYLogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onaMaster,is basedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
TheBUSYoutputsontheIDT71V321RAMmasteraretotem-poletype
outputsanddonotrequirepull-upresistorstooperate.IftheseRAMsare
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