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IDT7204L50TP 参数 Datasheet PDF下载

IDT7204L50TP图片预览
型号: IDT7204L50TP
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS异步FIFO 2048× 9 , 4096 ×9 , 8192 ×9和16384 ×9 [CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9]
分类和应用: 存储内存集成电路光电二极管先进先出芯片时钟
文件页数/大小: 14 页 / 151 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Continued)
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Military
7203S/L40
7204S/L40
Com'l & Mil.
7203S/L50
7204S/L50
7205L50
7206L50
Min.
65
15
50
10
15
5
65
50
15
30
5
65
50
50
15
65
50
50
15
50
50
50
10
15
15
50
30
65
65
65
45
45
45
45
65
65
50
50
7203S/L65
7204S/L65
Military
(2)
7203S/L80
7204S/L80
7203S/L120
7204S/L120
Symbol
f
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RSR
t
EFL
t
HFH
, t
FFH
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Parameters
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(3)
Read LOW to Data Bus LOW
(4)
Write HIGH to Data Bus Low-Z
(4, 5)
Data Valid from Read HIGH
Read HIGH to Data Bus High-Z
(4)
Write Cycle Time
Write Pulse Width
(3)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(3)
Reset Set-up Time
(4)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(3)
Min.
50
10
40
5
10
5
50
40
10
20
0
50
40
40
10
50
40
40
10
40
40
40
10
15
Max.
20
40
25
50
50
50
35
35
35
35
50
50
40
40
Max. Min.
80
15
65
10
15
5
80
65
15
30
10
80
65
65
15
80
65
65
15
65
65
65
10
15
Max. Min.
12.5
65
30
80
80
80
60
60
60
60
80
80
65
65
100
20
80
10
20
5
100
80
20
40
10
100
80
80
20
100
80
80
20
80
80
80
10
15
Max. Min.
10
80
30
100
100
100
60
60
60
60
100
100
80
80
140
20
120
10
20
5
140
120
20
40
10
140
120
120
20
140
120
120
20
120
120
120
10
15
Max.
7
120
35
140
140
140
60
60
60
60
140
140
120
120
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2661 tbl 06
Retransmit Set-up Time
(4)
Retransmit Recovery Time
Reset to
EF
LOW
Reset to
HF
and
FF
HIGH
Retransmit LOW to Flags Valid
Read LOW to
EF
Flag LOW
Read HIGH to
FF
HIGH
Read Pulse Width after
EF
HIGH
Write HIGH to
EF
HIGH
Write LOW to
FF
LOW
Write LOW to
HF
LOW
Read HIGH to
HF
HIGH
Write Pulse Width after
FF
HIGH
Read/Write LOW to
XO
LOW
Read/Write HIGH to
XO
HIGH
XI
XI
XI
Pulse Width
(3)
Recovery Time
Set-up Time
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
5.04
5