IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-
First-Out (FIFO) memories with clocked read and write controls and a flexible
Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user
benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (D
n
) and a data output port (Q
n
), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN
is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
PIN CONFIGURATIONS
INDEX
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
WCLK
PRS
MRS
LD
FWFT/SI
FF/IR
V
CC
PAF
GND
OW
FS0
HF
GND
FS1
BE
IP
BM
V
CC
PAE
PFM
EF/OR
RM
GND
RCLK
REN
RT
WEN
SEN
DNC
(1)
V
CC
DNC
(1)
IW
D35
D34
D33
D32
V
CC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
V
CC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
V
CC
D12
GND
D11
D10
D9
D8
D7
D6
GND
D5
D4
D3
V
CC
D2
D1
D0
GND
Q0
Q1
Q2
Q3
Q4
Q5
GND
Q6
V
CC
Q7
Q8
Q9
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
OE
V
CC
V
CC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
V
CC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
V
CC
V
CC
Q15
Q14
Q13
Q12
GND
Q11
Q10
4667 drw 02
NOTE:
1. DNC = Do Not Connect.
TQFP (PK128-1, order code: PF)
TOP VIEW
2
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