Functional Description
IOM R -2
Data Communication (MONITOR1)
Control (MONITOR1)
V/D - Module
ISAC R -S
PEB 2085/86
V/D - Module
R
ARCOFI PSB 2160
ARCOFI R -SP PSB 2165
R
ITAC PSB 2110
µC
µC
ITS00869
Figure 36
Examples of MONITOR Channel Applications in IOM®-2 TE Mode
The MONITOR channel operates on an asynchronous basis. While data transfers on the bus
take place synchronized to frame sync, the flow of data is controlled by a handshake procedure
using the MONITOR Channel Receive (MR0 or 1) and MONITOR Channel Transmit (MX0 or
1) bits. For example: data is placed onto the MONITOR channel and the MX bit is activated.
This data will be transmitted repeatedly once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
The microprocessor may either enforce a "1" (idle) in MR, MX by setting the control bit MRC1,
0 or MXC1, 0 to "0" (MONITOR Control Register MOCR), or enable the control of these bits
internally by the ISAC-S according to the MONITOR channel protocol. Thus, before a data
exchange can begin, the control bit MRC(1, 0) or MXC(1, 0) should be set to "1" by the
microprocessor.
The MONITOR channel protocol is illustrated in figure 37. Since the protocol is identical in
MONITOR channel 0 and MONITOR channel 1 (available in TE mode only), the index 0 or 1
has been left out in the illustration.
The relevant status bits are:
MONITOR Channel Data Received MDR (MDR0, MDR1)
MONITOR Channel End of Reception MER (MER0, MER1)
for the reception of MONITOR data, and
MONITOR Channel Data Acknowledged MDA (MDA0, MDA1)
MONITOR Channel Data Abort MAB (MAB0, MAB1)
for the transmission of MONITOR data (Register: MOSR)
In addition, the status bit:
MONITOR Channel Active MAC (MAC0, MAC1)
indicates whether a transmission is in progress (Register: STAR).
Semiconductor Group
72
INFINEON [ Infineon ]
