Functional Description
non-TE). It can be accessed by an external layer-2 device e.g. to control the layer-1
activation/deactivation procedures. C/I0 channel access may be arbitrated via the TIC bus
access protocol in the IOM-2 terminal timing mode (SPCR:SPM=0). In this case the
arbitration is done in C/I channel 2 (see
figure 29).
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2) and
register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits long.
A listing and explanation of the layer-1 C/I codes can be found in
chapter 3.4.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated anytime a change occurs (ISTA:CISQ). A new code must be found in two
consecutive IOM frames to be considered valid and to trigger a C/I code change interrupt
status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2) A second C/I channel (called C/I1) can be used to convey real time status information
between the ISAC-S and various non-layer-1 peripheral devices e.g. PSB 2160 ARCOFI.
The channel consists of six bits in each direction. It is available only in the IOM-2 TE timing
mode (see
figure 29).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received C/I1
code is indicated by an interrupt status without double last look criterion.
Semiconductor Group
75
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