IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 34. Upper-Memory Chip Select Register
15
1
14 13 12
LB2–LB0
11
10 9 8
Reserved
7
DA
6
0
5 4 3
Reserved
2
R2
1
0
R1–R0
Bit [15]—Reserved → Set to 1.
Bits [14–12]—LB2–LB0 Lower Boundary → These bits determine the bottom of the
memory accessed by the ucs_n chip selects. The UMCS Block-Size Programming Values
shown below list the possible block-size configurations (a 512-Kbyte maximum).
UMCS Block-Size Programming Values
Memory
Starting
Block Size Address LB2–LB0 Comments
64K
F0000h
111b
Default
128K
E0000h
110b
–
256K
C0000h
100b
–
512K
80000h
000b
–
Bits [11–8]—Reserved.
Bit [7]—DA → Disable Address. When set to 1, the address bus is disabled and the
address is not driven on the address bus when ucs_n is asserted, providing some measure
of power saving. When 0, the address is driven onto the address bus (ad15–ad0) during
the address phase of a bus cycle when ucs_n is asserted. This bit is set to 0 at reset.
–
If bhe_n/aden_n (IA186EM) is held at 0 during the rising edge of res_n, the address
bus is always driven, regardless of the setting.
Bit [6]—Reserved → Set to 0.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 Ready Mode → When set to 1, the external ready is ignored. When 0, it is
required. The value of the R1–R0 bits determines the number of wait states inserted.
Bits [1–0]—R1–R0 Wait-State Value → The value of these bits determines the number of
wait states inserted into an access to the lcs_n memory area. This number ranges from 0
to 3 (R1–R0 = 00b to 11b).
5.1.19 SPBAUD (088h)
Serial Port BAUD Rate Divisor Register. The value in this register determines the number of
internal processor cycles in one phase (half-period) of the 32 x serial clock. The contents of
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