IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 37. Serial Port Receive Data Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
RDATA
Bits [15–8]—Reserved.
Bits [7–0]—RDATA → Holds valid data while the RDR bit of the status register is set.
5.1.21 SPTD (084h)
Serial Port Transmit Data Register. Data is written to this register by software, with the values to
be transmitted by the serial port. Double buffering of the transmitter allows for the transmission
of data from the transmit shift register (no software access) while the next data are written into
the transmit register.
The THRE bit in the Serial Port Status register indicates whether there is valid data in the SPDT
register. The THRE bit must be a 1 before writing data to this register to prevent overwriting
valid data that is already in the SPDT register. The value of the SPTD register is undefined at
reset (see Table 38).
Table 38. Serial Port Transmit Data Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
TDATA
Bits [15–8]—Reserved.
Bits [7–0]—TDATA → Holds the data to be transmitted.
5.1.22 SPSTS (082h)
Serial Port STatuS Register. This register stores information concerning the current status of the
port. The status bits are described below.
The value of the SPSTS register is undefined at reset (see Table 39).
Table 39. Serial Port Status Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
TEMT THRE RDR BRKI FER PER OER
Bits [15–7]—Reserved → Set to 0.
Bit [6]—TEMT Transmitter Empty → When both the transmit shift register and the
transmit register are empty, this bit is set indicating to software that it is safe to disable
the transmitter. This bit is read-only.
®
IA211050831-19
UNCONTROLLED WHEN PRINTED OR COPIED
http://www.Innovasic.com
Customer Support:
Page 74 of 146
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
