IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Bit [5]—THRE Transmit Holding Register Empty → When this bit is 1, the
corresponding transmit holding register is ready to accept data. This is a read-only bit.
Bit [4]—RDR Receive Data Ready → When this bit is 1, the respective SPRD register
contains valid data. This is a read/write bit and can be reset only by reading the
corresponding receive register.
Bit [3]—BRKI Break Interrupt → This bit indicates that a break has been received when
this bit is set to 1 and causes a serial port interrupt request.
Note: This bit should be reset by software.
Bit [2]—FER Framing Error Detected → When the receiver samples the rxd line as low
when a stop bit is expected (line high) a framing error is generated setting this bit.
Note: This bit should be reset by software.
Bit [1]—PER Parity Error Detected → When a parity error is detected in either mode 1 or
3, this bit is set.
Note: This bit should be reset by software.
Bit [0]—OER Overrun Error Detected → When new data overwrites valid data in the
receive register (because it has not been read) an overrun error is detected setting this bit.
Note: This bit should be reset by software.
5.1.23 SPCT (080h)
Serial Port ConTrol Register. This register controls both transmit and receive parts of the serial
port. The value of the SPCT register is 0000h at reset (see Table 40).
Table 40. Serial Port Control Register
15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TXIE RXIE LOOP BRK BRKVAL PMODE WLGN STP TMODE RSIE RMODE
Bits [15–12]—Reserved → Set to 0.
Bit [11]—TXIE Transmitter Ready Interrupt Enable → This bit enables the generation of
an interrupt request whenever the transmit holding register is empty (THRE Bit [1]). The
respective port does not generate interrupts when this bit is 0. Interrupts continue to be
generated as long as THRE and the TXIE are 1.
®
IA211050831-19
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