IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 66. In-Service Register (Master Mode)
15
14 13 12
Reserved
11
10
SPI
9
WD
8
7
6 5
I4–I0
4
3
2
D1–D0
1
Reserved
0
TMR
Bits [15–11]—Reserved.
Bit [10]—SPI Serial Port Interrupt Request → This is the serial port 0 interrupt state.
Bit [9]—WD Watchdog Timer Interrupt In-Service Request → This bit is the In-Service
state of the Watchdog Timer.
Bits [8–4]—I4–I0 Interrupt Requests → Setting any of these bits to 1 indicates that the
relevant interrupt has a pending interrupt.
Bits [3–2]—D1–D0 DMA Channel Interrupt In-Service → This bit is the In-Service state
of the respective DMA channel.
Bit [1]—Reserved.
Bit [0]—TMR Timer Interrupt Request → This is the timer interrupt state and is the
logical OR of the timer interrupt requests. Setting this bit to 1 indicates that the timer
control unit has a pending interrupt.
5.1.45 INSERV (02ch) (Slave Mode)
This is a read-only register and such a read supplies the status of the interrupt request bits
presented to the interrupt controller.
When an internal interrupt request (D1, D0, TMR2, TMR1, and TMR0) occurs, the respective bit
is set to 1. The internally generated interrupt acknowledge resets these bits. The REQST
register contains 0000h on reset (see Table 67).
Table 67. In-Service Register (Slave Mode)
15
14
13
12 11 10
Reserved
9
8
7
6
5
TMR2
4
TMR1
3
2
D1–D0
1
Reserved
0
TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Timer 2 Interrupt In Service → Timer 2 is being serviced when this bit is
set to 1.
Bit [4]—TMR1 Timer 1 Interrupt In Service → Timer 1 is being serviced when this bit is
set to 1.
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