IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Bits [3–2]—D1–D0 DMA Channel Interrupt In Service → The respective DMA channel
is being serviced when this bit is set to 1.
Bit [1]—Reserved.
Bit [0]—TMR0 Timer Interrupt In Service → Timer 0 is being serviced when this bit is
set to 1.
5.1.46 PRIMSK (02ah) (Master and Slave Mode)
PRIority MaSK Register. This register contains a value that sets the minimum priority level at
which an interrupt can be generated by a maskable interrupt. The PRIMSK register contains
0007h on reset (see Table 68).
Table 68. Priority Mask Register
15
14
13
12
11 10 9 8
Reserved
7
6
5
4
3
2
1
0
PRM2–PRM0
Bits [15–3]—Reserved → Set to 0.
Bits [2–0]—PRM2–PRM0 Priority Field Mask → This three-bit field sets the minimum
priority necessary for a maskable interrupt to generate an interrupt. Any maskable
interrupt with a numerically higher value than that contained by these three bits is
masked. The values of PR2–PR0 are shown below.
Values of PR2–PR0 by Priority
Priority
PR2–PR0
(High) 0
000b
1
001b
2
010b
3
011b
4
100b
5
101b
6
110b
(Low) 7
111b
Any unmasked interrupt can generate an interrupt if the priority level is set to 7. On the
other hand, if the priority level is set to say 4, only unmasked interrupts with a priority of
0 to 5 are permitted to generate interrupts.
5.1.47 IMASK (028h) (Master Mode)
Interrupt MASK Register. The interrupt mask register is read/write. Setting a bit in this register
has the same effect as setting the MSK bit in the corresponding interrupt control register. Setting
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