IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
a bit to 1 masks the interrupt. The interrupt request is enabled when the corresponding bit is set
to 0. The IMASK register contains 07fdh on reset (see Table 69).
Table 69. Interrupt MASK Register (Master Mode)
15
14 13 12
Reserved
11
10
SPI
9
WD
8
7
6 5
I4–I0
4
3
2
D1–D0
1
Reserved
0
TMR
Bits [15–11]—Reserved.
Bit [10]—SPI Serial Port Interrupt Mask → Setting this bit to 1 is an indication that the
asynchronous serial port interrupt is masked.
Bit [9]—WD Watchdog Timer Interrupt In-Service Request → Setting this bit to 1
indicates that the Watchdog Timer interrupt is masked.
Bits [8–4]—I4–I0 Interrupt Mask → Setting any of these bits to 1 is an indication that the
relevant interrupt is masked.
Bits [3–2]—D1–D0 DMA Channel Interrupt Mask → Setting this bit to 1 is an indication
that the respective DMA channel interrupt is masked.
Bit [1]—Reserved.
Bit [0]—TMR Timer Interrupt Mask → When set to 1, it indicates that the timer control
unit interrupt is masked.
5.1.48 IMASK (028h) (Slave Mode)
Interrupt MASK Register. The interrupt mask register is read/write. Setting a bit in this register
is effectively the same as setting the MSK bit in the corresponding interrupt control register.
Setting a bit to 1 masks the interrupt request. The interrupt request is enabled when the
corresponding bit is set to 0. The IMASK register contains 003dh on reset (see Table 70).
Table 70. Interrupt MASK Register (Slave Mode)
15
14
13
12 11 10
Reserved
9
8
7
6
5
TMR2
4
TMR1
3
2
D1–D0
1
Reserved
0
TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Timer 2 Interrupt Mask → This bit provides an indication of the state of
the mask bit in the Timer Interrupt Control register. When set to 1, it indicates that the
interrupt request is masked.
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