IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
Description
The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a
CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The
following paragraphs will further describe this system block diagram and design in more detail.
TIMER
PRESCALER
TIMER/
COUNTER
OSC1
OSC2
RESET_N
TIMER CONTROL
OSCILLATOR
LI
IRQ_N
PA0
B0
ACCUMULATOR
8
PORT
A
REG
DATA
DIR
REG
INDEX
REGISTER
8
X
CONDITION
CODE
5 REGISTER CC
STACK
POINTER
6
SP
PROGRAM
COUNTER
HIGH PCH
5
PROGRAM
COUNTER
LOW PCL
8
ALU
ADDRESS
DRIVE
A
CPU
CONTROL
MUX
BUS
DRIVE
B1
B2
B3
B4
B5
B6
B7
MULTIPLEXED
ADDRESS
DATA
BUS
PA0
PA1
PA2
PORT
A
I/O
LINES
PA3
PA4
PA5
PA6
PA7
CPU
PB0
PB1
PB2
PORT
B
I/O
LINES
PB3
PB4
PB5
PB6
PB7
PORT
B
REG
DATA
DIR
REG
A8
A9
A10
A11
A12
ADDRESS
BUS
AS
112x8
RAM
BUS
CONTROL
DS
RW_N
ADDRESS STROBE
DATA STROBE
READ/WRITE
Figure 1. System Block Diagram
Copyright
©
2007
©
IA211081401-03
www.Innovasic.com
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