E
Mode
Read
Output Disable
READ-ONLY
Standby
Read
READ/WRITE Output Disable
Standby
(5)
Write
28F010
Table 2. 28F010 Bus Operations
V
PP(1)
V
PPL
V
PPL
V
PPL
V
PPL
V
PPL
V
PPH
V
PPH
V
PPH
V
PPH
A
0
A
0
X
X
V
IL
V
IH
A
0
X
X
A
0
A
9
A
9
X
X
V
ID(3)
V
ID(3)
A
9
X
X
A
9
CE#
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
OE# WE#
V
IL
V
IH
X
V
IL
V
IL
V
IL
V
IH
X
V
IH
V
IH
V
IH
X
V
IH
V
IH
V
IH
V
IH
X
V
IL
DQ
0
–DQ
7
Data Out
Tri-State
Tri-State
Data = 89H
Data = B4H
Data Out
(4)
Tri-State
Tri-State
Data In
(6)
Intelligent Identifier (Mfr)
(2)
Intelligent Identifier (Device)
(2)
NOTES:
1. Refer to
DC Characteristics.
When V
PP
= V
PPL
memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. V
ID
is the intelligent identifier high voltage. Refer to
DC Characteristics.
4. Read operations with V
PP
= V
PPH
may access array data or the intelligent identifier codes.
5. With V
PP
at high voltage, the standby current equals I
CC
+ I
PP
(standby).
6. Refer to Table 3 for valid data-in during a write operation.
7. X can be V
IL
or V
IH
.
2.2
Write Protection
2.2.1
2.2.1.1
BUS OPERATIONS
Read
The command register is only active when V
PP
is at
high voltage. Depending upon the application, the
system designer may choose to make the V
PP
power supply switchable—available only when
memory updates are desired. When V
PP
= V
PPL
, the
contents of the register default to the Read
command, making the 28F010 a read-only memory.
In this mode, the memory contents cannot be
altered.
Or, the system designer may choose to “hardwire”
V
PP
, making the high voltage supply constantly
available. In this case, all command register
functions are inhibited whenever V
CC
is below the
write lockout voltage V
LKO
. (See Section 3.4,
Power-Up/Down Protection
.) The 28F010 is
designed to accommodate either design practice,
and to encourage optimization of the processor
memory interface.
The two-step program/erase write sequence to the
command register provides additional software
write protections.
The 28F010 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins, independent
of device selection. Refer to the AC read timing
waveforms.
When V
PP
is high (V
PPH
), the read operation can be
used to access array data, to output the intelligent
identifier codes, and to access data for
program/erase verification. When V
PP
is low (V
PPL
),
the read operation can
only
access the array data.
2.2.1.2
Output Disable
With OE# at a logic-high level (V
IH
), output from the
device is disabled. Output pins are placed in a high-
impedance state.
9
INTEL [ INTEL CORPORATION ]
