8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
The Command User Interface (CUI) serves
as the interface between the microprocessor
or microcontroller and the internal
operation of the boot block flash memory
products. The internal Write State Machine
(WSM) automatically executes the
algorithms and timings necessary for
program and erase operations, including
verifications, thereby unburdening the
microprocessor or microcontroller of these
tasks. The Status Register (SR) indicates the
status of the WSM and whether it
successfully completed the desired program
or erase operation.
Program and erase automation allows
program and erase operations to be
executed using an industry-standard two-
write command sequence to the CUI. Data
writes are performed in word (28F800
family) or byte (28F800 or 28F008B
families) increments. Each byte or word in
the flash memory can be programmed
independently of other memory locations,
unlike erases, which erase all locations
within a block simultaneously.
The 8-Mbit SmartVoltage boot block flash
memory family is also designed with an
Automatic Power Savings (APS) feature
which minimizes system battery current
drain, allowing for very low power designs.
To provide even greater power savings, the
boot block family includes a deep power-
down mode which minimizes power
consumption by turning most of the flash
memory’s circuitry off. This mode is
controlled by the RP# pin and its usage is
discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides
protection against unwanted command
writes due to invalid system bus conditions
that may occur during system reset and
power-up/down sequences. For example,
6
when the flash memory powers-up, it
automatically defaults to the read array
mode, but during a warm system reset,
where power continues uninterrupted to the
system components, the flash memory
could remain in a non-read mode, such as
erase. Consequently, the system Reset
signal should be tied to RP# to reset the
memory to normal read mode upon
activation of the Reset signal (see Section
3.6).
The 28F800 provides both byte-wide or
word-wide input/output, which is
controlled by the BYTE# pin. Please see
Table 2 and Figure 13 for a detailed
description of BYTE# operations,
especially the usage of the
DQ
15
/A
–1
pin.
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INTEL [ INTEL CORPORATION ]
