IS41C16256
IS41LV16256
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
I
IL
I
IO
V
OH
V
OL
I
CC
1
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Stand-by Current: TTL
Test Condition
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
I
OH
= –2.5 mA
I
OL
= +2.1 mA
RAS, LCAS, UCAS
≥
V
IH
Commercial
Industrial
Commercial
Industrial
RAS, LCAS, UCAS
≥
V
CC
– 0.2V
RAS, LCAS, UCAS,
Address Cycling, t
RC
= t
RC
(min.)
RAS
= V
IL
,
LCAS, UCAS,
Cycling t
PC
= t
PC
(min.)
RAS
Cycling,
LCAS, UCAS
≥
V
IH
t
RC
= t
RC
(min.)
5V
5V
3V
3V
5V
3V
-35
-50
-60
-35
-50
-60
-35
-50
-60
-35
-50
-60
Speed
Min.
–10
–10
2.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ISSI
Max.
10
10
—
0.4
3
4
2
3
2
1
230
180
170
220
170
160
230
180
170
230
180
170
µA
µA
V
V
mA
®
Unit
I
CC
2
I
CC
3
Stand-by Current: CMOS
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
Refresh Current:
RAS-Only
(2,3)
Average Power Supply Current
mA
mA
I
CC
4
mA
I
CC
5
mA
I
CC
6
Refresh Current:
RAS, LCAS, UCAS
Cycling
(2,3,5)
CBR
t
RC
= t
RC
(min.)
Average Power Supply Current
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. J
06/29/00
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
