IS62WV25616ALL, IS62WV25616BLL
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS1 Controlled,
OE
= HIGH or LOW)
t
WC
ISSI
®
ADDRESS
t
SCS1
t
HA
CS1
t
AW
WE
LB, UB
t
SA
t
HZWE
t
PWE
t
PWB
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CS1
and
WE
inputs and at
least one of the
LB
and
UB
inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
WRITE CYCLE NO. 2
(WE Controlled:
OE
is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
SCS1
t
HA
CS1
t
AW
WE
t
PWE
LB, UB
t
SA
t
HZWE
HIGH-Z
t
LZWE
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
05/02/05
9