ML145053
LANSDALE Semiconductor, Inc.
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Guaranteed
Limit
Figure
Symbol
Parameter
Unit
1
f
Clock Frequency, SCLK
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
0
MHz
Note 1
2.1
Note: Refer to t , t
wH wL
below
1
1
t
Minimum Clock High Time, SCLK
Minimum Clock Low Time, SCLK
Maximum Propagation Delay, SCLK to D
190
190
125
10
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
wH
t
wL
, t
1, 7
1, 7
2, 7
2, 7
3
t
PLH PHL
out
t
h
Minimum Hold Time, SCLK to D
out
t
, t
PLZ PHZ
, t
PZL PZH
Maximum Propagation Delay, CS to D
High-Z
150
2.3
out
out
t
Maximum Propagation Delay, CS to D
Driven
t
Minimum Setup Time, D to SCLK
in
Minimum Hold Time, SCLK to D
in
100
0
su
3
t
h
t
d
4, 7, 8
5
Maximum Delay Time, EOC to D
out
(MSB)
100
2.425
Note 2
t
Minimum Setup Time, CS to SCLK
su
–
t
Minimum Time Required Between 10th SCLK Falling Edge ( 0.8 V) and
CS to Allow a Conversion
CSd
–
t
Maximum Delay Between 10th SCLK Falling Edge ( 2 V) and CS to
Abort a Conversion
9
µs
CAs
5
6, 8
1
t
Minimum Hold Time, Last SCLK to CS
0
ns
h
t
Maximum Propagation Delay, 10th SCLK to EOC
2.35
µs
PHL
t , t
Maximum Input Rise and Fall Times
SCLK
D , CS
in
1
10
ms
µs
r f
1, 4, 6 – 8
–
t
, t
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
300
ns
TLH THL
C
AN0 – AN4
55
15
pF
in
SCLK, CS, D
in
–
C
Maximum Three-State Output Capacitance
D
15
pF
out
out
NOTES:
1. After the 10th SCLK falling edge (≥2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 18.5 µs.
2. A CS edge may be received immediately after an active transition on the EOC pin.
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