ML145053
LANSDALE Semiconductor, Inc.
on the first four rising edges of SCLK, and the previous 10-bit from unselected channels to a selected channel and leakage
conversion result is shifted out on the first nine falling edges
of SCLK. After the fourth rising edge of SCLK, the new mux
address is available; therefore, on the next edge of SCLK (the
fourth falling edge), the analog input voltage on the selected
currents through the ESD protection diodes on the selected
channel occur. These leakage currents cause an offset voltage
to appear across any series source resistance on the selected
channel. Therefore, any source resistance greater than 1 kΩ
mux input begins charging the RC DAC and continues to do so (Lansdale test condition) may induce errors in excess of guar-
until the tenth falling edge of SCLK. After this tenth SCLK
edge, the analog input voltage is disabled from the RC DAC
anteed specifications.There are three tests available that verify
the functionality of all the control logic as well as the succes-
and the RC DAC begins the “hold” portion of the A/D conver- sive approximation comparator. These tests are performed by
sion sequence. Also upon this tenth SCLK edge, control of the addressing $B, $C, or $D and they convert a voltage of (V
+
ref
internal circuitry is transferred to the internal clock oscillator
which drives the successive approximation logic to complete
the conversion. If 16 SCLK cycles are used during each trans-
fer, then there is a constraint on the minimum SCLK frequen-
cy. Specifically, there must be at least one rising edge on
SCLK before the A/D conversion is complete. If the SCLK
frequency is too low and a rising edge does not occur during
the conversion, the chip is thrown out of sync with the proces-
sor and CS needs to be toggled in order to restore proper oper-
V
AG
)/2, V , or V , respectively. The voltages are obtained
AG ref
internally by sampling V or V
ments of the RC DAC during the sample phase. Addressing
$B, $C, or $D produces an output of $200 (half scale), $000,
onto the appropriate ele-
AG
ref
or $3FF (full scale), respectively, if the converter is functioning
properly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip)
onV , V , V , or V
.
DD SS ref AG
ation. If 10 SCLKs are used per transfer, then there is no lower POWER AND REFERENCE PINS
frequency limit on SCLK. Also note that if the ADC is operat-
ed such that CS is inactive high between transfers, then the
number of SCLK cycles per transfer can be anything between
10 and 16 cycles, but the “rising edge” constraint is still in
effect if more than 10 SCLKs are used. (If CS stays active low
for multiple transfers, the number of SCLK cycles must be
either 10 or 16.)
V
and V
DD
SS
Device Supply Pins (Pins 7 and 14)
V
is normally connected to digital ground; V
is con-
DD
SS
nected to a positive digital supply voltage. Low frequency
(V – V ) variations over the range of 4.5 to 5.5 volts do
DD
SS
not affect the A/D accuracy. (See the Operations Ranges Table
for restrictions on V and V relative to V and V .)
ref AG DD SS
EOC
Excessive inductance in the V or V lines, as on automat-
ic test equipment, may cause A/D offsets > 1 LSB. Use of a
DD
SS
End-of-Conversion Output (Pin 1)
EOC goes low on the tenth falling edge of SCLK. A low-to-
high transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
0.1 µF bypass capacitor across these pins is recommended.
V
and V
ref
AG
Analog Reference Voltage Pins (Pins 8 and 9)
ANALOG INPUTS AND TEST MODES
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input volt-
AN0 through AN4
Analog Multiplexer Inputs (Pins 2 – 6)
ages ≥ V produce a full scale output and input voltages ≤
ref
V
AG
produce an output of zero. CAUTION: The analog input
The input AN0 is addressed by loading $0 into the mux
address register. AN1 is addressed by $1, AN2 by $2, AN3 by
$3, and AN4 by $4. Table 2 shows the input format for a 16-bit free as possible to avoid degradation of the A/D conversion.
stream. The mux features a break-before-make switching struc- Ideally, V and V should be single-point connected to the
ture to minimize noise injection into the analog inputs. The
source resistance driving these inputs must be ≤ 1 kΩ. During
normal operation, leakage currents through the analog mux
voltage must be ≥ V and ≤ V . The A/D conversion result
SS DD
is ratiometric to V – V . V and V must be as noise-
ref AG ref AG
ref
AG
voltage supply driving the system's transducers. Use of a 0.22
µF bypass capacitor across these pins is strongly urged.
Page 7 of 15
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