ML145053
LANSDALE Semiconductor, Inc.
CS
HIGH IMPEDANCE
D9
D
D9–MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
out
1
2
3
4
5
6
7
8
9
10
1
SCLK
D
in
A3
MSB
EOC
A/D CONVERSION
INITERVAL
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
RE-INITIALIZE
INITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS
MUST BE HIGH ON POWER UP
CS
D
D9–MSB
D8
A2
D7
A1
D6
A0
D5
D4
D3
D2
D1
D0
D9
out
LOW LEVEL
1
2
3
4
5
6
7
8
9
10
1
SCLK
D
in
A3
A3
MSB
EOC
A/D CONVERSION
INITERVAL
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
INITIALIZE
Figure 10. Timing for 10-Clock Transfer Not Using CS
NOTES:
1. D9, D8, D7, D6, D5, …, D0 = the result of the previous A/D conversion.
2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
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