ML145170
LANSDALE
Semiconductor,
Inc.
Frequency of fV > fR or Phase of fV Leading fR: positive
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: negative
pulses from high impedance
Frequency and Phase of fV = fR: essentially high–impedance
state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the C
register. If desired, PDout can be forced to the high–impedance
state by utilization of the disable feature in the C register
(patented).
φ
R and
φ
V
Double–Ended
Phase/Frequency
Detector Outputs (Pins 14,
15)
These outputs can be combined externally to generate a loop
error signal. Through use of a Motorola patented technique,
the detector’s dead zone has been eliminated. Therefore, the
phase/frequency detector is characterized by a linear transfer
function. The operation of the phase/frequency detector is
described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR:
φ
V = neg-
ative pulses,
φ
R = essentially high
Frequency of fV < fR or Phase of fV Lagging fR:
φ
V =
essentially high,
φR
= negative pulses
Frequency and Phase of fV = fR:
φ
V and
φ
R remain essen-
tially high, except for a small minimum time period when both
pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR:
φ
R = nega-
tive pulses,
φ
V = essentially high
Frequency of fV < fR or Phase of fV Lagging fR:
φ
R = essen-
tially high,
φ
V = negative pulses
Frequency and Phase of fV = fR:
φ
V and
φ
R remain essen-
tially high, except for a small minimum time period when both
pulse low in phase
These outputs can be enabled, disabled, and interchanged via
the C register (patented)
LD
Lock Detector Output (Pin 11)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when fV
and fR are out of phase or different frequencies (See Figure
17).
This output can be enabled and disabled via the C register
(patented). Upon power up, on–chip initialization circuitry dis-
ables LD to a static low logic level to prevent a false “lock”
signal. If unused, LD should be disabled and left open.
POWER
SUPPLY
VDD
Most
Positive
Supply
Potential
(Pin 16)
This pin may range from 2.7 to 5.5 V with respect to VSS.
For optimum performance, VDD should be bypassed to VSS
using low–inductance capacitor(s) mounted very close to the
device. Lead lengths on the capacitor(s) should be minimized.
(The very fast switching speed of the device causes current
spikes on the power leads.)
VSS
Most Negative Supply
Potential
(Pin 12)
This pin is usually ground. For measurement purposes, the
VSS pin is tied to a ground plane.
Figure 13. Reset Sequence
NOTE:
This initialization
sequence
is
usually
not necessary because the on–chip power–on reset circuit performs the initialization
function. However, this initialization
sequence
must be
used
immediately
after
power
up
if control of the CLK pin is not
possible. That is, if CLK (Pin 7) toggles or floats
upon
power
up, use
the
above sequence
to reset the device.
Also,
use
this
sequence
if power is momentarily interrupted
such
thhat the
supply
voltage to the device is reduced to below
h
2.7 V, but not down to
at
least 1 V (for example, the
supply
drops down to 2 V). This is necessary because the on–chip
power–on reset is only
activated
when the
supply
ramps
up
from
a
voltage below
approximately
1.0 V.
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