ML145170
LANSDALE
Semiconductor,
Inc.
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
*At this point, the new byte is transferred to the C register
and stored.
No other registers
are affected.
C7–POL:
Selects the output polarity of the phase/frequency detectors. When
set
high, this bit inverts
PDout
and
interchanges the
φ
R funtion with
φ
V
as
depicted in Figure 17. Also
see
the phase
detector output pin description for more information. This bit is cleared low
at
power
up.
Selects which phase/frequency detector is to be
used.
When
set
high, enables the output of
phase/frequency detector A (PDout)
and
disables phase/frequency detector B by forcing
φ
R
and
φ
V to the
static
high
state.
When cleared low, phase/frequency detector B is enabled (φ R
and
φ
V)
and
phase/frequency detector A is disabled with PDout forced to the high–impedance
state.
This bit is cleared low
at
power
up.
Enables the lock detector output when
set
high. When the bit is cleared low, the LD output is
forced to
a static
low level. This bit is cleared low
at
power
up.
Reference output controls which determine the REFout characteristics
as shown
below. Upon
power
up,
the bits
are
initialized
such
that OSCin/8 is
selected.
C6–PDA/B:
C5–LDE:
C4–C2, OSC2–OSC0:
C4
0
0
0
0
1
1
1
1
C3
0
0
1
1
0
0
1
1
C2
0
1
0
1
0
1
0
1
REF
out
Frequency
DC (Static Low)
OSC
in
OSC
in
/2
OSC
in
/4
OSC
in
/8 (POR Default)
OSC
in
/16
OSC
in
/8
OSC
in
/16
C1–fVE:
C0–fRE:
Enables the fV output when
set
high. When cleared low, the fV output is forced to
a static
low
level. The bit is cleared low
upon
power
up.
Enables the fR output when
set
high. When cleared low, the fR output is forced to
a static
low
level. The bit is cleared low
upon
power
up.
Page 11 of 26
www.lansdale.com
Issue A
LANSDALE [ LANSDALE SEMICONDUCTOR INC. ]
