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GAL18V10-15LP 参数 Datasheet PDF下载

GAL18V10-15LP图片预览
型号: GAL18V10-15LP
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用: 可编程逻辑器件光电二极管输入元件时钟
文件页数/大小: 16 页 / 267 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications
GAL18V10B
AC Switching Characteristics
Over Recommended Operating Conditions
COM
TEST
PARAM.
COND.
1
COM
COM
COM
DESCRIPTION
Input or I/O to Comb. Output
Clock to Output Delay
Clock to Feedback Delay
Setup Time, Input or Fdbk before Clk↑
Hold Time, Input or Fdbk after Clk↑
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
Maximum Clock Frequency with
No Feedback
Clock Pulse Duration, High
Clock Pulse Duration, Low
Input or I/O to Output Enabled
Input or I/O to Output Disabled
Input or I/O to Asynch. Reset of Reg.
Asynch. Reset Pulse Duration
Asynch. Reset to Clk↑ Recovery Time
Synch. Preset to Clk↑ Recovery Time
5.5
0
90.9
-7
-10
-15
-20
UNITS
ns
ns
ns
ns
ns
MHz
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
7.5
5.5
3.5
6
0
76.9
10
7
3.5
8
0
55.5
15
10
7
12
0
41.6
20
12
10
t
pd
t
co
t
cf
2
t
su
t
h
A
A
A
f
max
3
A
A
111
111
105
105
66.7
66.7
45.4
62.5
MHz
MHz
t
wh
t
wl
t
en
t
dis
t
ar
t
arw
t
arr
t
spr
B
C
A
4
4
8
8
10
8
8
13
4
4
8
8
10
10
9
13
6
6
10
10
10
15
15
20
8
8
15
15
12
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
1) Refer to
Switching Test Conditions
section.
2) Calculated from
fmax
with internal feedback. Refer to
fmax Description
section.
3) Refer to
fmax Description
section.
Capacitance (T
A
= 25°C, f = 1.0 MHz)
SYMBOL
C
I
C
I/O
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
8
8
UNITS
pF
pF
TEST CONDITIONS
V
CC
= 5.0V, V
I
= 2.0V
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
7