Specifications ispGDX Family
External Timing Parameters
Over Recommended Operating Conditions
-5
-7
TEST1
COND.
PARAMETER
DESCRIPTION
#
UNITS
MIN. MAX. MIN. MAX.
A
A
–
1
2
3
4
5
6
7
8
9
Data Propagation Delay from any I/O pin to any I/O pin
Data Propagation Delay from MUXsel Inputs to any Output
tpd
tsel
–
–
5.0
6.5
–
–
–
7.0
9.0
–
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Clock Frequency with External Feedback
fmax(ext)
tsu1
tsu2
th
tgco1
tgco2
tco1
tco2
ten
(
)
111
4.0
4.0
0.0
–
80.0
5.5
5.5
0.0
–
tsu2+tgco1
–
Input Latch or Register Setup Time before any Clk
–
–
–
Output Latch or Register MUX Data Setup Time before any Clk
Latch or Register Hold Time after any Clk
–
–
–
–
–
A
A
A
A
B
C
B
C
–
Output Latch or Register Clk (from Yx) to Output Delay
Input Latch or Register Clk (from Yx) to Output Delay
Output Latch or Register Clk (from I/O pin) to Output Delay
5
7.0
11.0
9.0
13.0
8.5
8.5
12.0
12.0
–
–
8.5
6.0
9.5
6.0
6.0
9.0
9.0
–
–
10 Input Latch or Register Clock (from I/O pin) to Output Delay
11 Input to Output Enable
–
–
–
–
12 Input to Output Disable
tdis
–
–
13 Test OE Output Enable
ttoeen
ttoedis
twh
twl
trst
trw
tsl
tsk
–
–
14 Test OE Output Disable
–
–
15 Clock Pulse Duration, High
3.5
3.5
–
5.0
5.0
–
–
16 Clock Pulse Duration, Low
–
–
–
17 Register Reset Delay from RESET Low
18 Reset pulse width
14.0
–
18.0
–
–
10.0
–
14.0
–
A
A
19 Output Delay Adder for Output Timings Using Slow Slew Rate
20 Output Skew (tgco1 across chip)
5.0
0.5
7.0
0.5
–
–
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
ispGDX timings are specified with a GRP load (fanout) of
four I/O cells. The figure at right shows the Maximum ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK, MUXsel0-1). Global Clock signals, which do
not use the GRP, have no fanout delay adder.
Maximum ∆ GRP Delay vs. I/O Cell Fanout
10
8
6
4
2
0 4 10
20 30
40 50 60 70
I/O Cell Fanout
8
LATTICE [ LATTICE SEMICONDUCTOR ]
