Specifications ispGDX Family
1
Internal Timing Parameters
Over Recommended Operating Conditions
-5
-7
2
1
PARAMETER #
DESCRIPTION
MIN. MAX. MIN. MAX. UNITS
Inputs
t
21 Input Buffer Delay
22 GRP Delay
—
—
0.7
2.0
—
—
1.3
2.5
ns
ns
io
GRP
t
grp
MUX
t
t
23 I/O Cell MUX A/B/C/D Data Delay
24 I/O Cell MUX A/B/C/D Data Select
—
—
1.0
2.5
—
—
1.4
3.4
ns
ns
muxd
muxs
Register
t
t
t
t
t
25 I/O Latch Delay
—
—
—
—
—
1.6
1.6
2.4
1.6
0.7
—
—
—
—
—
2.2
1.8
3.6
2.2
1.0
ns
ns
ns
ns
ns
iolat
iosu
ioh
26 I/O Register Setup Time Before Clock
27 I/O Register Hold Time After Clock
28 I/O Register Clock to Output Delay
29 I/O Reset to Output Delay
ioco
ior
Data Path
t
t
t
t
t
t
t
30 I/O Register Feedback Delay
31 I/O Register Bypass Delay
—
—
—
—
—
—
—
0.2
0.4
0.1
1.1
2.1
4.1
5.1
—
—
—
—
—
—
—
0.3
0.6
0.7
1.2
3.2
5.1
7.1
ns
ns
ns
ns
ns
ns
ns
rfdbk
iobp
32 I/O Register Output Buffer Delay
ioob
(Yx Clk) 33 I/O Register Data Input MUX Delay
(I/O Clk) 34 I/O Register Data Input MUX Delay
muxc
muxc
(Yx Clk) 35 I/O Register I/O Input MUX Delay
(I/O Clk) 36 I/O Register I/O Input MUX Delay
iod
iod
Outputs
t
t
t
t
t
t
37 Output Buffer Delay
—
—
—
—
—
—
0.9
5.9
0.8
0.8
2.5
8.2
—
—
—
—
—
—
1.3
8.3
ns
ns
ns
ns
ns
ns
ob
38 Output Buffer Delay, Slow Slew
39 I/O Cell OE to Output Enabled
40 I/O Cell OE to Output Disabled
41 Global Output Enable Delay
42 Test OE Enable Delay
obs
oen
oedis
goe
toe
1.1
1.1
3.6
10.9
Clocks
t
t
43 I/O Clock Delay
—
—
0.7
2.4
—
—
1.0
2.8
ns
ns
cio
44 Clock Delay, Y0/1/2/3
gy0/1/2/3
Global Reset
t
45 Global Reset to I/O Register/Latch
—
12.3
—
15.0
ns
gr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
9
LATTICE [ LATTICE SEMICONDUCTOR ]
