Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
-180
MIN. MAX. MIN. MAX. MIN. MAX.
-150
-135
2
PARAMETER
#
DESCRIPTION
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
–
0.6
1.1
–
–
0.6
1.3
–
–
1.1
2.4
ns
ns
21 Dedicated Input Delay
GRP
22 GRP Delay
–
0.7
–
0.7
–
1.3
ns
tgrp
GLB
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
2.3
3.1
3.6
4.1
4.8
0.2
–
–
–
2.6
3.1
4.3
4.6
5.0
0.0
–
–
–
3.6
3.6
5.0
5.1
5.6
0.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
–
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
–
–
28 GLB Register Bypass Delay
–
–
–
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
0.5
1.8
–
0.7
1.8
–
0.3
3.0
–
–
–
–
0.7
1.0
2.8
5.9
0.8
1.2
2.9
6.9
0.7
1.1
4.4
6.4
–
–
–
–
–
–
tptre
–
–
–
tptoe
tptck
ORP
2.5 3.8
2.5 4.1 2.9 5.2
36 ORP Delay
–
–
0.7
0.2
–
–
0.8
0.3
–
–
1.3
0.3
ns
ns
torp
37 ORP Bypass Delay
torpbp
Outputs
tob
tsl
toen
38 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.2
10.0
3.2
ns
ns
ns
ns
ns
1.2
10.0
2.8
1.3
10.0
2.8
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
3.2
todis
tgoe
2.8
2.8
2.8
2.2
2.2
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.9
1.9
2.1
2.1
2.3 2.3
2.3 2.3
ns
ns
tgy0
1.9
1.9
2.1
2.1
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
–
–
–
6.4
ns
4.1
4.7
Table 2-0036C-180/2032
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
LATTICE [ LATTICE SEMICONDUCTOR ]
