Specifications ispLSI 2032/A
ispLSI 2032/A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
#24
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0
0491/2000
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min)
= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
2.1 ns = (0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
1.5 ns = (0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
tco
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20+ #22+ #35) + (#31) + (#36 + #38)
7.7 ns = (0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Table 2- 0042-16/2032
9
LATTICE [ LATTICE SEMICONDUCTOR ]
