Specifications
ispLSI 2032/A
Internal Timing Parameters
1
Over Recommended Operating Conditions
PARAMETER
Inputs
21 Dedicated Input Delay
22 GRP Delay
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay
3
28 GLB Register Bypass Delay
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
35 GLB Product Term Clock Delay
36 ORP Delay
–
–
3.4
1.7
–
–
4.8
#
2
DESCRIPTION
-110
-80
UNITS
MIN. MAX. MIN. MAX.
–
1.7
–
2.2
GRP
D
ES
IG
–
4.9
4.8
6.2
6.8
7.5
0.1
–
–
0.6
1.8
5.9
7.1
7.0
1.5
0.5
1.2
10.0
4.0
4.0
3.0
3.2
3.2
9.0
–
–
–
–
–
–
–
t
grp
GLB
N
2.6
7.2
7.2
8.8
9.2
10.2
0.0
–
–
0.4
2.2
8.8
12.8
9.5
2.1
0.6
2.4
10.0
6.4
6.4
5.6
4.6
4.6
12.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ORP
37 ORP Bypass Delay
03
t
orp
t
orpbp
Outputs
2E
t
4ptbpc
t
4ptbpr
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
EW
–
–
0.5
4.0
–
–
–
–
4.0
–
–
–
–
–
–
–
3.2
3.2
–
–
–
0.1
6.0
–
–
–
–
5.5
–
–
–
–
–
–
–
4.6
4.6
–
34 GLB Product Term Output Enable to I/O Cell Delay
Clocks
U
Global Reset
t
gr
SE
t
gy0
t
gy1/2
is
p
t
ob
t
sl
t
oen
t
odis
t
goe
38 Output Buffer Delay
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
45 Global Reset to GLB
LS
39 Output Slew Limited Delay Adder
I2
FO
R
N
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036C-110/2032
8
S
t
io
t
din
20 Input Buffer Delay
ns
ns
LATTICE [ LATTICE SEMICONDUCTOR ]
