Lattice Semiconductor
Introduction
LatticeXP Family Data Sheet
Introduction
The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a
single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs.
The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-
ogy. With this technology, expensive external configuration memories are not required and designs are secured
from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.
The ispLEVER
®
design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
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LATTICE [ LATTICE SEMICONDUCTOR ]
