Lattice Semiconductor
Figure 2-1. LatticeXP Top Level Block Diagram
Programmable I/O Cell
(PIC) includes sysIO
Interface
Architecture
LatticeXP Family Data Sheet
sysMEM Embedded
Block RAM (EBR)
Non-volatile Memory
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
PFU and PFF Blocks
The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
Slice 1
Slice 2
Slice 3
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
To
Routing
2-2
LATTICE [ LATTICE SEMICONDUCTOR ]
