Lattice Semiconductor
Slice
Architecture
LatticeXP Family Data Sheet
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Figure 2-3. Slice Diagram
To / From
Different slice / PFU Fast Carry In (FCI)
Slice
OFX1
A1
B1
C1
D1
CO
F1
F
SUM
D
LUT4 &
CARRY
CI
FF/
Latch
Q1
To
Routing
From
Routing
M1
M0
LUT
Expansion
Mux
OFX0
A0
B0
CO
C0
D0
LUT4 &
CARRY
CI
F
SUM
OFX0
D
F0
FF/
Latch
Q0
Control Signals
selected and
inverted per
slice in routing
CE
CLK
LSR
Note: Some interslice signals
are not shown.
To / From
Different slice / PFU Fast Carry Out (FCO)
2-3
LATTICE [ LATTICE SEMICONDUCTOR ]
