LFXP6C-4FN256C 参数 Datasheet PDF下载

Lattice Semiconductor

Figure 2-5. Primary Clock Sources

From Routing

Clock Input

From Routing

Architecture

LatticeXP Family Data Sheet

PLL Input

PLL

PLL

PLL Input

Clock Input

20 Primary Clock Sources

To Quadrant Clock Selection

Clock Input

PLL Input

PLL

PLL

PLL Input

From Routing

Clock Input

From Routing

Note: Smaller devices have two PLLs.

Secondary Clock Sources

LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at

every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary

clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6.

2-7