LFXP6C-4FN256C 参数 Datasheet PDF下载

Lattice Semiconductor

Figure 2-6. Secondary Clock Sources

From

Routing

From

Routing

Clock

Input

From

Routing

Architecture

LatticeXP Family Data Sheet

From

Routing

From Routing

From Routing

From Routing

From Routing

Clock Input

20 Secondary Clock Sources

To Quadrant Clock Selection

Clock Input

From Routing

From Routing

From Routing

From Routing

From

Routing

From

Routing

Clock

Input

From

Routing

From

Routing

Clock Routing

The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-

work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this

clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-

8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-

9.

Figure 2-7. Per Quadrant Primary Clock Selection

20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing

1

DCS

2

DCS

2

4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant

1. Smaller devices have fewer PLL related lines.

2. Dynamic clock select.

2-8