Lattice Semiconductor
Table 2-4. PFU Modes of Operation
Logic
LUT 4x8 or
MUX 2x1 x 8
LUT 5x4 or
MUX 4x1 x 4
LUT 6x 2 or
MUX 8x1 x 2
LUT 7x1 or
MUX 16x1 x 1
Ripple
2-bit Add x 4
2-bit Sub x 4
2-bit Counter x 4
2-bit Comp x 4
RAM
1
SPR16x2 x 4
DPR16x2 x 2
SPR16x4 x 2
DPR16x4 x 1
SPR16x8 x 1
Architecture
LatticeXP Family Data Sheet
ROM
ROM16x1 x 8
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
1. These modes are not available in PFF blocks
Routing
There are many resources provided in the LatticeXP devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. The
x2 and x6 resources are buffered allowing both short and long connections routing between PFUs.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeXP devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. Lat-
ticeXP devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four
dedicated clock inputs, one on each side of the device. Figure 2-5 shows the 20 primary clock sources.
2-6
LATTICE [ LATTICE SEMICONDUCTOR ]
